1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device, and more particularly relates to a method for manufacturing a flash memory device.
2. Description of the Related Art
Since a flash memory device can be programmed and erased by electronic operations, such as applying different voltages, it has become a widely used memory module. Depending on the gate structure, flash memories can be divided into a stacked-gate flash memory or a split-gate flash memory. Although the stacked-gate flash memory occupies less area, an over-erasing problem sometimes occurs during the operation. Therefore, the split-gate flash memory is currently used to eliminate the over-erasing problem.
A flash memory device usually includes a control gate and a floating gate. The control gate serves the function of a select or access transistor, while the floating gate serves as a storage device. Generally, when the capacitive coupling ratio between the control gate and the floating gate is greater, the reading and/or writing speed of memory will be faster. Although the thin inter-gate dielectric layer may improve the capacitive coupling ratio between the control gate and the floating gate, the thin inter-gate dielectric layer may result in current leakage. Thus, the memory devices may suffer a data retention issue. In addition, the control gate needs more word-line voltages in order to increase the reading and erasing speed of the memory device.
Therefore, it is necessary to create a flash memory device having greater capacitive coupling ratio between the control gate and the floating gate for enhancing efficiencies of writing and erasing and decreasing the operating voltage, while concurrently having good retention of data.